VLSI System Design
( P04-315-01_TEACHING LABORATORY )
TIMETABLE
LIST OF EXPERIMENTS
3rd YEAR LAB
FPGA
OpenLane
1. VLSI Physical Design (Student Pack)
Welcome to
VLSI System Design Laboratory
This lab was constructed under ECE Department FKE and currently supervised by Dr. Suhaila binti Ishak as the Laboratory Academic Coordinator. An Assistant Engineer has been positioned to ensure the smoothness of the lab operations. This website provides the information you need. Hopefully this web can guide you in preparing your experiment and useful for your reference.
LABORATORY ACADEMIC COORDINATOR
LABORATORY STAFF
Dr Suhaila binti Ishak
Laboratory Academic Coordinator
Email: suhailaisaak@utm.my
Mr. Yazid Bin Mohamed Bain
Assistant Engineer
Email: yazidmbain@utm.my





