Welcome

ECE2025

2nd International Conference on Electronic and Computer Engineering

Holiday Inn Johor Bahru City Centre

21-22 August 2025

 

Conference Tracks

Machine Learning and Pattern Recognition

Nanotechnology and Advanced Materials

Biosensors, Biosignals, and Biomedical Imaging

VLSI and Computing Architecture

About ECE2025

The 2nd International Conference on Electronic and Computer Engineering (ECE2025) will be held on 21-22 Aug 2025 at Johor Bahru. The conference is organized by the Department of Electronic and Computer Engineering, Faculty of Electrical Engineering, Universiti Teknologi Malaysia and co-sponsored by the IEEE Electron Devices Society (EDS) Malaysia Chapter.

ECE2025 aims at bringing together researchers from industry and academia from all over the world to gather and explore various issues and trends in the field of Electronics and Computer Engineering. This conference provides opportunities for the researchers to share their research and experiences, establish research relations, and globally collaborate among them.

The ECE2025 is a prominent international forum on four main tracks which are Machine Learning and Pattern Recognition, Nanotechnology and Advanced Materials, Biosensors, Biosignals and Biomedical Imaging and VLSI & Computer Architecture.

Why ECE2025?

Hybrid Conference

Virtual presentation available for Overseas participants

Scopus Indexed

Presented papers will be submited for publication in IEEE Xplore Digital Library

Organizers

Gold Sponsors

Silver Sponsors

Keynote Speakers

Prof. Dr. Ir. Mohammad Faizal Bin Ahmad Fauzi

Professor, Faculty of Artificial Intelligence and Engineering, Multimedia University

Towards Precision Medicine: Machine learning and Image Processing in Digital Pathology

Digital pathology is the management and interpretation of pathology information in a digital environment that enables better, faster and cheaper diagnosis and prognosis of cancer and other diseases. With the advent of whole-slide imaging, the field of digital and computational pathology has gained a lot of traction, especially among the machine learning and image processing communities. Precision medicine, or personalized medicine, on the other hand aims to tailor treatments to individuals based on their unique characteristics, moving away from the one-size-fits-all approach of traditional medicine. In this lecture, I will discuss our work in developing computer-aided systems for breast cancer precision medicine from whole-slide pathology images.

Prof. Dr. T. Nandha Kumar

Professor, Department of Electrical and Electronic Engineering, University of Nottingham Malaysia

In-Memory Computing Across Memory Technologies — SRAM, DRAM, and Memristors: Design Insights and Challenges

Traditional computational systems have long relied on the Von Neumann architecture, which separates memory and processing units. This architecture requires frequent data transfers between memory and the central processing unit (CPU), leading to a performance bottleneck known as the “memory wall.” 

The growing demands of artificial intelligence (AI), big data, and cloud-scale applications have shifted computational workloads from being compute-intensive to memory-intensive, intensifying the strain on data movement and memory bandwidth.

In this context, In-Memory Computing (IMC) has emerged as a promising paradigm that enables computations—particularly data-heavy operations such as matrix multiplications—to be performed directly within memory arrays. This approach reduces data movement, enhances performance, and improves energy efficiency.

This talk will present an overview of IMC techniques implemented using SRAM, DRAM, and the emerging Resistive RAM (ReRAM or Memristors). It will explore their underlying design principles, compare their architectural and circuit-level trade-offs, and discuss the challenges of scalability, reliability, and integration with conventional computing systems.

Mr. Michael Liew Woon Chin

CTO & Chief Architect, StarFive Technology International Sdn. Bhd.

AI-Powered SOC Design: Unlocking Innovation, Efficiency and Complexity Management

The semiconductor industry is undergoing a profound transformation driven by increasing design complexity, accelerated product life cycles, and the growing need for innovation at scale. At the heart of this evolution lies the potential of Artificial Intelligence (AI) to revolutionize System-on-Chip (SoC) design. This speech explores how AI-driven methodologies empower design houses to stay competitive and agile in the face of mounting challenges.

As SoCs become more heterogeneous and densely packed with IP blocks—CPU clusters, AI accelerators, security engines, and high-speed interfaces—the complexity of design, verification, and optimization has grown exponentially. Traditional design methods are increasingly insufficient to manage this scale and pace. AI introduces intelligent automation across the SoC lifecycle—from RTL generation and floorplanning to timing closure and functional verification—resulting in faster iterations, improved performance-per-watt, and reduced time-to-market.

We have embraced this transformation firsthand through the development of our innovative SoCs from IOT, Edge, Client to Data Center SOC, each built using AI-assisted design techniques. Leveraging these approaches has significantly improved design quality, enhanced engineering efficiency, and enabled us to meet aggressive delivery schedules. By integrating AI into key phases of our development process, we’ve achieved higher confidence in first-pass silicon while empowering our design teams to focus on architectural innovation and product differentiation.

Ultimately, this presentation positions AI-augmented SoC design not just as a technological enhancement, but as a strategic necessity for design houses navigating the pressures of innovation, shrinking development windows, and increasingly complex chip architectures. Attendees will gain insight into real-world examples, current AI-enabled EDA tools, and how embracing these techniques can redefine the future of semiconductor design.

Important Dates

15 Jan 2025

Call for paper

15 June 2025

(Extended)
15 Apr 2025
Deadline submission of full paper

15 June 2025

Notification of acceptance

30 June 2025

Early bird registration deadline

14 July 2025

Registration

18 July 2025

Submission of camera-ready paper

21-22 Aug 2025

Conference day

Submission Closing In

Day(s)

:

Hour(s)

:

Minute(s)

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*Accepted and presented papers will be submitted for publication in the IEEE Xplore Digital Library and for indexing in Scopus, subject to IEEE’s quality review requirements.

Early Bird Registration

Student

(IEEE Member)

RM900

(USD210)

Regular

(IEEE Member)

RM1000

(USD250)

Non-Member

 

RM1200

(USD300)

Non-Presenter

 

RM600

(USD150)

Normal Registration

Student

(IEEE Member)

RM1100

(USD260)

Regular

(IEEE Member)

RM1200

(USD300)

Non-Member

 

RM1400

(USD350)

Non-Presenter

 

RM600

(USD150)

*Student authors with multiple accepted papers must register one of the papers as full registration and the others as student registration.

**Overseas participants may opt for online presentation.

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